EOI Intercepts

An intercept is defined for processor events (specifically, memory accesses) that indicate the end of interrupt (EOI) for a level-triggered fixed interrupt. An EOI intercept is the expected (eventual) response by the child to a parent that asserts a level-triggered interrupt through a call to the HvAssertVirtualInterrupt hypercall function. The intercept is delivered at the instruction boundary following the instruction that issued the EOI.

To improve performance, the child should reduce the number of EOI intercepts. The child can eliminate most EOI intercepts if the guest operating system leaves a marker when the guest operating system performs an EOI. However, EOI intercepts are required in either of the following situations:

• A level-triggered interrupt is indicated by EOI, since the hypervisor needs to either send an EOI message for the physical APIC (in case of the root partition) or send an EOI message (in case of a non-root partition) when the guest performs an EOI.

• A lower-priority interrupt is pending, since the hypervisor needs to re-evaluate interrupts when the guest performs an EOI.

For more information about intercepts, see Hypervisor Intercepts.

APIC Assist Page Register

The hypervisor provides a virtual APIC assist page per virtual processor, which is overlaid on the guest operating system GPA space. The operating system has read and write access to the virtual APIC assist page. The operating system specifies the location of the overlay page (in GPA space) by writing to the virtual APIC assist page MSR. The virtual APIC assist page MSR is defined as follows:

#define HV_X64_MSR_APIC_ASSIST_PAGE   (0x40000073)

The format of the virtual APIC assist page MSR is shown as follows:

The guest operating system uses a HV_X64_MSR_APIC_ASSIST_CONTENTS union to program a virtual APIC assist page MSR.

Currently, the only defined field in the virtual APIC assist page is the EOI Assist field. The EOI Assist field resides at offset 0 of the overlay page and is DWORD sized. The format of the EOI assist field is shown as follows

The operating system performs an EOI by atomically writing zero to the EOI Assist field of the virtual APIC assist page and checking whether the "No EOI required" field was previously zero. If the "No EOI required" field was previously zero, the operating system must write to the HV_X64_APIC_EOI MSR thereby triggering an intercept into the hypervisor. The following code is recommended to perform an EOI:

lea rcx, [VirtualApicAssistVa]
btc [rcx], 0
jc NoEoiRequired
mov ecx, HV_X64_APIC_EOI
wrmsr
NoEoiRequired:

The hypervisor sets the "No EOI required" bit when the hypervisor injects a virtual interrupt if the following conditions are satisfied:

• The virtual interrupt is edge triggered.

• There are no lower priority interrupts pending.

If, at a later time, a lower-priority interrupt is requested, the hypervisor clears the "No EOI required" bit such that a subsequent EOI causes an intercept.

In case of nested interrupts, the EOI intercept is avoided only for the highest-priority interrupt. This is necessary since no count is maintained for the number of EOIs performed by the operating system. Therefore, only the first EOI can be avoided. Since the first EOI clears the "No EOI Required" bit, the next EOI generates an intercept. However, because nested interrupts are rare, this scenario is not a problem in the common case.

Note that devices and the I/O APIC (physical or synthetic) must not be notified of an EOI for an edge-triggered interrupt; the hypervisor intercepts such EOIs only to update the virtual APIC state. In some cases, the virtual APIC state can be updated. In such cases, the "NoEoiRequired" bit is set by the hypervisor and indicates to the guest operating system that an EOI intercept is not necessary. Subsequently, the hypervisor can derive the state of the local APIC depending on the current value of the "NoEoiRequired" bit.

Enabling and disabling this enlightenment (that is, setting and clearing the "No EOI Required" bit) can be done at any time independently of the interrupt activity and the APIC state at that moment. While the enlightenment is enabled, conventional EOIs can still be performed irrespective of the "No EOI required" value. However, they will not realize the performance benefit of the enlightenment.

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Build date: 11/16/2013