Hardware Management Data Types
The hypervisor defines data types to manage the aspects of physical hardware that are described in the following sections:
Logical Processors
The hypervisor defines logical processors by a 32-bit index type as follows:
typedef UINT32 HV_LOGICAL_PROCESSOR_INDEX;
Power States MSRs
Each logical processor has an associated power state. The root partition can change the power state as the root partition's policy dictates. The root partition uses power management configuration model-specific registers (MSR) to communicate the recipe for power state transitions for each logical processor, and for informing the hypervisor when the hypervisor should trigger a power state change.
The hypervisor supports transitions to and from power states C1, C2, and C3.
The root partition configures power state transitions by using MSRs that are associated with each logical processor. Each of the power states has an associated pair of MSRs that are shown in the following table.
MSR address | Register name | Function |
---|---|---|
0x400000D1 |
HV_X64_MSR_POWER_STATE_CONFIG_C1 |
Configuration register for power state C1 |
0x400000C1 |
HV_X64_MSR_POWER_STATE_TRIGGER_C1 |
Trigger register for power state C1 |
0x400000D2 |
HV_X64_MSR_POWER_STATE_CONFIG_C2 |
Configuration register for power state C2 |
0x400000C2 |
HV_X64_MSR_POWER_STATE_TRIGGER_C2 |
Trigger register for power state C2 |
0x400000D3 |
HV_X64_MSR_POWER_STATE_CONFIG_C3 |
Configuration register for power state C3 |
0x400000C3 |
HV_X64_MSR_POWER_STATE_TRIGGER_C3 |
Trigger register for power state C3 |
The power state configuration registers are read-and-write registers that the power management partition uses to specify the recipe to transition to and from the corresponding power state. The power management partition uses the HV_X64_MSR_POWER_STATE_CONFIG union to configure the bits of the power state configuration registers.
Power state trigger registers are read-only registers that cause the process to enter the corresponding power state. The power management partition uses the HV_X64_MSR_POWER_STATE_TRIGGER union to configure the bits of the power state trigger registers.
Logical Processor Run Time
A 64-bit quantity called a run time is associated with each logical processor. The hypervisor defines the run time as the number of 100-nanosecond time units that have elapsed since the logical processor was last reset (through the APIC) and during which the logical processor actively executed code (either guest code or hypervisor code). When a logical processor has no code to run or enters a low-power or offline state, the logical processor's run time counter effectively stops.
The following type is used for the run-time value.
typedef UINT64 HV_NANO100_TIME; typedef HV_NANO100_TIME *PHV_NANO100_TIME;
Logical Processor Run Time Groups
The hypervisor allows logical processors to be grouped together to form run time groups. A logical processor can only belong to at most one run time group; no overlaps are allowed. These groups provide software that are within the root partition the ability to determine whether any of a collection of logical processors have executed within a time range. This ability is useful in cases where multiple logical processors are connected to a single power plane and are treated as a single piece of hardware from a power management perspective.
To show how the hypervisor's run time accounting for individual logical processors and run time groups differs, consider the (admittedly contrived) case where four logical processors are each scheduled to run 25% of the time and their execution times do not overlap. In this case, the run time for the individual logical processors will increment 250ms for each second of actual elapsed time. The run time for the group will increment 1sec for each second of actual elapsed time because at least one logical processor within the group is running at all times.
Global Run Time
The hypervisor also maintains a global run time that starts when the hypervisor is booted. As with the logical processor run time, the global run time is recorded in 100ns time units.
System Reset MSR
The hypervisor defines the system-reset MSR as follows:
#define HV_X64_MSR_RESET 0x40000003
If the system-reset MSR is available to the guest operating system, the system-reset MSR is accessible from all of the partition's virtual processors. The system-reset MSR has the format that is shown in the following table. A HV_X64_MSR_RESET_CONTENTS union is used to encode a system-reset MSR.
63:1 | 0 |
---|---|
RsvdZ |
Reset |
The guest operating system always initially reads zero in the Reset field of the MSR. When the guest operating system writes one to the Reset field, the hypervisor will perform the requested reboot operation.
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Build date: 11/16/2013