Synthetic Timer MSRs
Synthetic timers are configured by using model-specific registers (MSRs) that are associated with each virtual processor. Each of the four synthetic timers has an associated pair of configuration and count MSRs as shown in the following table.
| MSR address | Register name | Function |
|---|---|---|
|
0x400000B0 |
HV_X64_MSR_STIMER0_CONFIG |
Configuration register for synthetic timer 0 |
|
0x400000B1 |
HV_X64_MSR_STIMER0_COUNT |
Expiration time or period for synthetic timer 0 |
|
0x400000B2 |
HV_X64_MSR_STIMER1_CONFIG |
Configuration register for synthetic timer 1 |
|
0x400000B3 |
HV_X64_MSR_STIMER1_COUNT |
Expiration time or period for synthetic timer 1 |
|
0x400000B4 |
HV_X64_MSR_STIMER2_CONFIG |
Configuration register for synthetic timer 2 |
|
0x400000B5 |
HX_X64_MSR_STIMER2_COUNT |
Expiration time or period for synthetic timer 2 |
|
0x400000B6 |
HV_X64_MSR_STIMER3_CONFIG |
Configuration register for synthetic timer 3 |
|
0x400000B7 |
HV_X64_MSR_STIMER3_COUNT |
Expiration time or period for synthetic timer 3 |
The following sections describe how the synthetic timer configuration and count MSRs are encoded:
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Build date: 11/16/2013