Hypervisor Memory Cache Control

The following sections describe how the hypervisor controls the memory cache:

Cacheability Settings

The hypervisor supports guest-defined cacheability settings for pages that are mapped within the guest's GVA space. For more information about available cacheability settings and their meanings, refer to the Intel or AMD documentation.

When a virtual processor accesses a page through its GVA space, the hypervisor honors the cache attribute bits (PAT, PWT, and PCD) within the guest page table entry that is used to map the page. These three bits are used as an index into the partition's page address type (PAT) register to look up the final cacheability setting for the page.

Pages that are accessed directly through the GPA space (for example, when paging is disabled because CR0.PG is cleared) use a cacheability that is defined by the MTRRs. If the hypervisor implementation does not support virtual MTRRs, write-back (WB) cacheability is assumed.

Mixing Cache Types between a Partition and the Hypervisor

Guests should be aware that some pages within their GPA space might be accessed by the hypervisor. The following page types represent some example:

• A page that contains input or output parameters for a hypercall

• All overlay pages that include the hypercall page, SynIC SIEF and SIM pages, and stats pages

The hypervisor always performs accesses to hypercall parameters and overlay pages by using the WB cacheability setting.

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Build date: 11/16/2013