Local APIC Virtualization

The hypervisor's local APIC virtualization might deviate from physical APIC operation in the following minor ways:

On physical systems, the IA32_APIC_BASE MSR can be different for each processor in the system. The hypervisor might require that this MSR contains the same value for all virtual processors within a partition. As such, all virtual processors within a partition might treat this MSR as a partition-wide value. If a virtual processor modifies this register, the value might effectively propagate to all virtual processors within the partition.
The IA32_APIC_BASE MSR defines a global enable bit for enabling or disabling the APIC. The virtualized APIC might always be enabled. If so, this bit will always be set to 1.
The hypervisor's local APIC might not be able to generate virtual system management interrupts (SMI).
The hypervisor might allow accesses only to the APIC's memory-mapped registers; these access types are performed by one of the instructions described in Local APIC Memory-mapped Accesses. Furthermore, the hypervisor might allow only accesses that are four bytes in size and aligned to four-byte boundaries. In such cases, if an unsupported access is attempted, the virtual processor will be suspended, and an unsupported feature error message will be delivered to the partition's parent.
If multiple virtual processors within a partition are assigned identical APIC identifiers, the behavior of targeted interrupt delivery is undefined. That is, the hypervisor is free to deliver the interrupt to just one virtual processor, all virtual processors with the specified APIC identifier, or no virtual processors. This situation is considered a guest programming error.
Some of the memory-mapped APIC registers might be accessed by way of virtual MSRs.

The Local APIC Memory-mapped Accesses and Local APIC MSR Accesses sections describe only those aspects of SynIC functionality that are extensions of the local APIC.

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Build date: 11/16/2013