Local APIC MSR Accesses

The hypervisor provides accelerated MSR access to high-usage memory-mapped APIC registers. These are the TPR, EOI, and ICR registers. The ICR-low and ICR-high registers are combined into one MSR.

MSR Address	Register Name	Function
0x40000070	HV_X64_MSR_EOI	Accesses the APIC EOI
0x40000071	HV_X64_MSR_ICR	Accesses the APIC ICR high and ICR low
0x40000072	HV_X64_MSR_TPR	Access the APIC TPR

For performance reasons, the guest operating system should follow the hypervisor recommendation for the usage of the APIC MSRs. For more information about usage of the APIC MSRs, see Microsoft Hypervisor CPUID Leaves.

The following sections show how these TPR, EOI, and ICR registers are encoded:

EOI Register

The EOI register is a write-only register. The hypervisor sets a value into the APIC EOI register. Attempts to read from this register will result in a #GP fault.

63:32	31:0
Ignored	EOI value

Bits	Description	Attributes
63:32	RsvdZ (reserved, should be zero)	Write
31:0	EOI value	Write

ICR Register

The values of ICR high and ICR low are read from or written into the corresponding APIC ICR high and low registers.

63:32	31:0
ICR high	ICR low

Bits	Description	Attributes
63:32	ICR high value	Read/write
31:0	ICR low value	Read/write

TPR Register

The value of the APIC TPR register is read or written.

63:8	7:0
RsvdZ	TPR value

Bits	Description	Attributes
63:8	RsvdZ (reserved, should be zero)	Read/write
7:0	TPR value	Read/write

Note The TPR MSR is intended to accelerate access to the TPR in 32-bit mode guest partitions. 64-bit mode guest partitions should set the TPR by way of CR8.

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Build date: 11/16/2013