Partition Properties

A parent partition can use partition properties to control aspects of its child partitions. After the parent partition calls the HvSetPartitionProperty function to set a property of a child partition, the property's value is constant unless and until the property is again modified by a caller that possesses sufficient privilege.

Properties are identified by a 32-bit code. The hypervisor defines property codes in the HV_PARTITION_PROPERTY_CODE enumeration.

Property values are each 64 bits in size. The hypervisor defines the property value data type as follows:


typedef UINT64 HV_PARTITION_PROPERTY, *PHV_PARTITION_PROPERTY;

Partition Virtual TLB Page Count

The hypervisor maintains a virtual translation look-aside buffer (TLB) for each virtual processor (for more information about a virtual TLB, see Hypervisor Virtual MMU). The memory that is available for the virtual TLB is reserved and allocated from the partition's memory pool. The HvPartitionPropertyVirtualTlbPageCount partition property defines the number of pages that are reserved for the TLB. This number can be modified dynamically. The hypervisor establishes a default value, which can be different for the root and other (non-root) partitions. The hypervisor also enforces minimum and maximum page count restrictions. If you attempt to set the page count outside of the restrictions, the hypervisor sets the value to the appropriate minimum or maximum value.

The following partition properties are read-only. A caller can call the HvGetPartitionProperty function to retrieve a read-only property's value.

Partition Processor Vendor

The HvPartitionPropertyProcessorVendor partition property defines the processor vendor of the platform that the partition was created on.

The codes are defined by the values in the HV_PROCESSOR_VENDOR enumeration.

Partition Processor Features

The HvPartitionPropertyProcessorFeatures partition property defines the processor features that are verified for migration compatibility when a virtual machine is restored. This property is used to enumerate or de-feature a partition's processor features so that platform migration can be performed.

The property is defined with the HV_PARTITION_PROCESSOR_FEATURES structure.

Partition Processor XSAVE Features

Similar to HvPartitionPropertyProcessorFeatures, the HvPartitionPropertyProcessorXsaveFeatures partition property defines the processor XSAVE-related features that are verified for migration compatibility when a virtual machine processor is restored. This property is used to enumerate or de-feature a partition's XSAVE features so that virtual machine migration can be performed.

The property is defined with the HV_PARTITION_PROCESSOR_XSAVE_FEATURES structure.

Partition Cache Line Flush Size

The HvPartitionPropertyProcessorCLFlushSize partition property defines the cache line flush size of the partition. This property is used to enumerate or specify a partition's processor cache line flush size so that virtual machine migration can be performed.

This property is a UINT64.

Partition Compatibility Mode

To allow a virtual machine to migrate between platforms of the same processor architecture but with differing processor feature sets and characteristics, the hypervisor defines the following partition properties for a compatibility virtual machine.

The HV_PARTITION_PROCESSOR_FEATURES_INTEL_COMPATIBILITY_MODE value defines, from the HV_PARTITION_PROCESSOR_FEATURES union, the processor features that are available in Intel compatibility mode:


#define HV_PARTITION_PROCESSOR_FEATURES_INTEL_COMPATIBILITY_MODE \
{   1,   /* Sse3Support */ \
    1,   /* LahfSahfSupport */ \
    0,   /* Ssse3Support */ \
    0,   /* Sse4_1Support */ \
    0,   /* Sse4_2Support */ \
    0,   /* Sse4aSupport */ \
    0,   /* Sse5Support */ \
    0,   /* PopCntSupport */ \
    1,   /* Cmpxchg16bSupport */ \
    0,   /* Altmovcr8Support */ \
    0,   /* LzcntSupport */ \
    0,   /* MisAlignSseSupport */ \
    0,   /* MmxExtSupport */ \
    0,   /* Amd3DNowSupport */ \
    0,   /* ExtendedAmd3DNowSupport */ \
    0,   /* Page1GBSupport */ \
    0    /* Reserved1 */ \
}

The HV_PARTITION_PROCESSOR_FEATURES_AMD_COMPATIBILITY_MODE value defines, from the HV_PARTITION_PROCESSOR_FEATURES union, the processor features that are available in AMD compatibility mode:


#define HV_PARTITION_PROCESSOR_FEATURES_AMD_COMPATIBILITY_MODE \
{ \
    1,   /* Sse3Support */ \
    1,   /* LahfSahfSupport */ \
    0,   /* Ssse3Support */ \
    0,   /* Sse4_1Support */ \
    0,   /* Sse4_2Support */ \
    0,   /* Sse4aSupport */ \
    0,   /* Sse5Support */ \
    0,   /* PopCntSupport */ \
    1,   /* Cmpxchg16bSupport */ \
    1,   /* Altmovcr8Support */ \
    0,   /* LzcntSupport */ \
    0,   /* MisAlignSseSupport */ \
    1,   /* MmxExtSupport */ \
    0,   /* Amd3DNowSupport */ \
    0,   /* ExtendedAmd3DNowSupport */ \
    0,   /* Page1GBSupport */ \
    0    /* Reserved1 */ \
}

The HV_PARTITION_PROCESSOR_XSAVE_FEATURES_INTEL_COMPATIBILITY_MODE value defines, from the HV_PARTITION_PROCESSOR_XSAVE_FEATURES union, the processor features that are avaialble in Intel compatibility mode:
Copy
#define HV_PARTITION_PROCESSOR_XSAVE_FEATURES_INTEL_COMPATIBILITY_MODE \ { \ 0, /* XsaveSupport */ \ 0, /* XsaveoptSupport */ \ 0, /* AvxSupport */ \ 0 /* Reserved1 */ \ }
The HV_PARTITION_PROCESSOR_XSAVE_FEATURES_AMD_COMPATIBILITY_MODE value defines, from the HV_PARTITION_PROCESSOR_XSAVE_FEATURES union, the processor features that are avaialble in AMD compatibility mode:
Copy
#define HV_PARTITION_PROCESSOR_XSAVE_FEATURES_AMD_COMPATIBILITY_MODE \ { \ 0, /* XsaveSupport */ \ 0, /* XsaveoptSupport */ \ 0, /* AvxSupport */ \ 0 /* Reserved1 */ \ }

The following constants define the processor cache line flush size for Intel and AMD compatibility mode:


#define HV_PARTITION_PROCESSOR_CL_FLUSHSIZE_INTEL_COMPATIBILITY_MODE (8)
#define HV_PARTITION_PROCESSOR_CL_FLUSHSIZE_AMD_COMPATIBILITY_MODE (8)

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Build date: 11/16/2013