HV_PARTITION_PROCESSOR_FEATURES union

The HV_PARTITION_PROCESSOR_FEATURES union identifies features of the processor.

Syntax

typedef union _HV_PARTITION_PROCESSOR_FEATURES {
  struct {
    UINT64 Sse3Support  :1;
    UINT64 LahfSahfSupport  :1;
    UINT64 Ssse3Support  :1;
    UINT64 Sse4_1Support  :1;
    UINT64 Sse4_2Support  :1;
    UINT64 Sse4aSupport  :1;
    UINT64 Sse5Support  :1;
    UINT64 PopCntSupport  :1;
    UINT64 Cmpxchg16bSupport  :1;
    UINT64 Altmovcr8Support  :1;
    UINT64 LzcntSupport  :1;
    UINT64 MisAlignSseSupport  :1;
    UINT64 MmxExtSupport  :1;
    UINT64 Amd3DNowSupport  :1;
    UINT64 ExtendedAmd3DNowSupport  :1;
    UINT64 Page1GBSupport  :1;
    UINT64 Reserved1  :48;
  };
  UINT64 AsUINT64;
} HV_PARTITION_PROCESSOR_FEATURES, *PHV_PARTITION_PROCESSOR_FEATURES;

Members

Sse3Support

A UINT64 value that specifies whether the processor supports Streaming SIMD Extensions 3 (SSE3). SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. The SSE3-support indication is set in the first bit of the 64-bit AsUINT64 member (0x0000000000000001).

LahfSahfSupport

A UINT64 value that specifies whether the processor supports the LAHF (load the 8085 equivalent flags into the AH register) and SAHF (store the AH register into the low order byte of the flag register) instructions. The indication for LAHF and SAHF support is set in the second bit of the 64-bit AsUINT64 member (0x0000000000000002).

Ssse3Support

A UINT64 value that specifies whether the processor supports Supplemental Streaming SIMD Extensions 3 (SSSE3). SSSE3 is the fourth iteration of the SSE instruction set. The SSSE3-support indication is set in the third bit of the 64-bit AsUINT64 member (0x0000000000000004).

Sse4_1Support

A UINT64 value that specifies whether the processor supports the SSE4.1 instruction set. SSE4.1 consists of 47 instructions that improve performance of media data manipulation. The SSE4.1-support indication is set in the fourth bit of the 64-bit AsUINT64 member (0x0000000000000008).

Sse4_2Support

A UINT64 value that specifies whether the processor supports the SSE4.2 instruction set. SSE4.2 consists of seven instructions that improve performance of text processing and some application-specific operations. The SSE4.2-support indication is set in the fifth bit of the 64-bit AsUINT64 member (0x0000000000000010).

Sse4aSupport

A UINT64 value that specifies whether the processor supports the SSE4a instruction set. SSE4a consists of four instructions from the SSE4 instruction set along with two additional SSE instructions. SSE4a is for unaligned SSE load-operation instructions (which formerly required 16-byte alignment). The SSE4a-support indication is set in the sixth bit of the 64-bit AsUINT64 member (0x0000000000000020).

Sse5Support

A UINT64 value that specifies whether the processor supports the SSE5 instruction set. SSE5 consists of 170 instructions (which includes 46 base instructions), many of which are designed to improve single-threaded performance. SSE5 is the fifth iteration of the SSE instruction set. The SSE5-support indication is set in the seventh bit of the 64-bit AsUINT64 member (0x0000000000000040).

PopCntSupport

A UINT64 value that specifies whether the processor supports the Population Count (PopCnt) instruction. PopCnt determines the number of set bits (bits with the value 1) in the input 64-bit value. The PopCnt-support indication is set in the eighth bit of the 64-bit AsUINT64 member (0x0000000000000080).

Cmpxchg16bSupport

A UINT64 value that specifies whether the processor supports the Cmpxchg16b instruction. Cmpxchg16b performs a 128-bit compare and exchange. The Cmpxchg16b-support indication is set in the ninth bit of the 64-bit AsUINT64 member (0x0000000000000100).

Altmovcr8Support

A UINT64 value that specifies whether the processor supports the Altmovcr8 instruction. The Altmovcr8-support indication is set in the tenth bit of the 64-bit AsUINT64 member (0x0000000000000200).

LzcntSupport

A UINT64 value that specifies whether the processor supports the Lzcnt instruction. The Lzcnt-support indication is set in the eleventh bit of the 64-bit AsUINT64 member (0x0000000000000400).

MisAlignSseSupport

A UINT64 value that specifies whether the processor supports the MisAlignSse instruction. The MisAlignSse-support indication is set in the twelfth bit of the 64-bit AsUINT64 member (0x0000000000000800).

MmxExtSupport

A UINT64 value that specifies whether the processor supports the MmxExt instruction. The MmxExt-support indication is set in the thirteenth bit of the 64-bit AsUINT64 member (0x0000000000001000).

Amd3DNowSupport

A UINT64 value that specifies whether the processor supports the Amd3DNow instruction. The Amd3DNow-support indication is set in the fourteenth bit of the 64-bit AsUINT64 member (0x0000000000002000).

ExtendedAmd3DNowSupport

A UINT64 value that specifies whether the processor supports the ExtendedAmd3DNow instruction. The ExtendedAmd3DNow-support indication is set in the fifteenth bit of the 64-bit AsUINT64 member (0x0000000000004000).

Page1GBSupport

A UINT64 value that specifies whether the processor supports the Page1GB instruction. The Page1GB-support indication is set in the sixteenth bit of the 64-bit AsUINT64 member (0x0000000000008000).

Reserved1

This member is reserved and should be set to zero. Setting this member to zero is equivalent to setting the remaining 48 bits of the 64-bit AsUINT64 member to zero (0xFFFFFFFFFFFF0000).

AsUINT64

A member in the union that can hold one 64-bit value that identifies features of the processor.

Remarks

The HV_PARTITION_PROCESSOR_FEATURES union is used to remove or add features.

Requirements

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Build date: 11/16/2013