Hypervisor Synthetic MSRs

0x40000000

HV_X64_MSR_GUEST_OS_ID

AccessHypercallMsrs

R/W

Identifies the guest operating system that runs in the partition.

0x40000001

HV_X64_MSR_HYPERCALL

AccessHypercallMsrs

R/W

Enables the hypercall interface.

0x40000002

HV_X64_MSR_VP_INDEX

AccessVpIndex

R

Specifies the virtual processor's index.

0x40000003

HV_X64_MSR_RESET

AccessResetMsr

R/W

Performs a hypervisor-controlled reboot operation.

0x40000010

HV_X64_MSR_VP_RUNTIME

AccessVpRuntimeMsr

R

Specifies the virtual processor's run time in 100ns units.

0x40000020

HV_X64_MSR_TIME_REF_COUNT

AccessPartitionReferenceCounter

R

Partition-wide reference counter.

0x40000021

HV_X64_MSR_REFERENCE_TSC

AccessPartitionReferenceCounter

R

Partition-wide reference time stamp counter.

0x40000070

HV_X64_MSR_EOI

AccessApicMsrs

W

Fast access to the APIC EOI register.

0x40000071

HV_X64_MSR_ICR

AccessApicMsrs

R/W

Fast access to the APIC ICR high and ICR low registers.

0x40000072

HV_X64_MSR_TPR

AccessApicMsrs

R/W

Fast access to the APIC TPR register (use CR8 in 64-bit mode).

0x40000073

HV_X64_MSR_APIC_ASSIST_PAGE

AccessApicMsrs

R/W

Enables EOI processing.

0x40000080

HV_X64_MSR_SCONTROL

AccessSynicMsrs

R/W

Controls specific behaviors of the synthetic interrupt controller.

0x40000081

HV_X64_MSR_SVERSION

AccessSynicMsrs

R

Specifies the SynIC version.

0x40000082

HV_X64_MSR_SIEFP

AccessSynicMsrs

R/W

Controls the base address of the synthetic interrupt event flag page.

0x40000083

HV_X64_MSR_SIMP

AccessSynicMsrs

R/W

Controls the base address of the synthetic interrupt parameter page.

0x40000084

HV_X64_MSR_EOM

AccessSynicMsrs

W

Indicates the end of message in the SynIC.

0x40000090

HV_X64_MSR_SINT0

AccessSynicMsrs

R/W

Configures synthetic interrupt source 0.

0x40000091

HV_X64_MSR_SINT1

AccessSynicMsrs

R/W

Configures synthetic interrupt source 1.

0x40000092

HV_X64_MSR_SINT2

AccessSynicMsrs

R/W

Configures synthetic interrupt source 2.

0x40000093

HV_X64_MSR_SINT3

AccessSynicMsrs

R/W

Configures synthetic interrupt source 3.

0x40000094

HV_X64_MSR_SINT4

AccessSynicMsrs

R/W

Configures synthetic interrupt source 4.

0x40000095

HV_X64_MSR_SINT5

AccessSynicMsrs

R/W

Configures synthetic interrupt source 5.

0x40000096

HV_X64_MSR_SINT6

AccessSynicMsrs

R/W

Configures synthetic interrupt source 6.

0x40000097

HV_X64_MSR_SINT7

AccessSynicMsrs

R/W

Configures synthetic interrupt source 7.

0x40000098

HV_X64_MSR_SINT8

AccessSynicMsrs

R/W

Configures synthetic interrupt source 8.

0x40000099

HV_X64_MSR_SINT9

AccessSynicMsrs

R/W

Configures synthetic interrupt source 9.

0x4000009A

HV_X64_MSR_SINT10

AccessSynicMsrs

R/W

Configures synthetic interrupt source 10.

0x4000009B

HV_X64_MSR_SINT11

AccessSynicMsrs

R/W

Configures synthetic interrupt source 11.

0x4000009C

HV_X64_MSR_SINT12

AccessSynicMsrs

R/W

Configures synthetic interrupt source 12.

0x4000009D

HV_X64_MSR_SINT13

AccessSynicMsrs

R/W

Configures synthetic interrupt source 13.

0x4000009E

HV_X64_MSR_SINT14

AccessSynicMsrs

R/W

Configures synthetic interrupt source 14.

0x4000009F

HV_X64_MSR_SINT15

AccessSynicMsrs

R/W

Configures synthetic interrupt source 15.

0x400000B0

HV_X64_MSR_STIMER0_CONFIG

AccessSyntheticTimerMsrs

R/W

Configuration register for synthetic timer 0.

0x400000B1

HV_X64_MSR_STIMER0_COUNT

AccessSyntheticTimerMsrs

R/W

Expiration time or period for synthetic timer 0.

0x400000B2

HV_X64_MSR_STIMER1_CONFIG

AccessSyntheticTimerMsrs

R/W

Configuration register for synthetic timer 1.

0x400000B3

HV_X64_MSR_STIMER1_COUNT

AccessSyntheticTimerMsrs

R/W

Expiration time or period for synthetic timer 1.

0x400000B4

HV_X64_MSR_STIMER2_CONFIG

AccessSyntheticTimerMsrs

R/W

Configuration register for synthetic timer 2.

0x400000B5

HV_X64_MSR_STIMER2_COUNT

AccessSyntheticTimerMsrs

R/W

Expiration time or period for synthetic timer 2.

0x400000B6

HV_X64_MSR_STIMER3_CONFIG

AccessSyntheticTimerMsrs

R/W

Configuration register for synthetic timer 3.

0x400000B7

HV_X64_MSR_STIMER3_COUNT

AccessSyntheticTimerMsrs

R/W

Expiration time or period for synthetic timer 3.

0x400000C1

HV_X64_MSR_POWER_STATE_TRIGGER_C1

CPUManagement

R

Trigger the transition to power state C1

0x400000C2

HV_X64_MSR_POWER_STATE_TRIGGER_C2

CPUManagement

R

Trigger the transition to power state C2

0x400000C3

HV_X64_MSR_POWER_STATE_TRIGGER_C3

CPUManagement

R

Trigger the transition to power state C3

0x400000D1

HV_X64_MSR_POWER_STATE_CONFIG_C1

CPUManagement

R/W

Configure the recipe for power state transitions to C1

0x400000D2

HV_X64_MSR_POWER_STATE_CONFIG_C2

CPUManagement

R/W

Configure the recipe for power state transitions to C2

0x400000D3

HV_X64_MSR_POWER_STATE_CONFIG_C3

CPUManagement

R/W

Configure the recipe for power state transitions to C3

0x400000E0

HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE

AccessStatsMsr

R/W

Map the guest's retail partition statistics page

0x400000E1

HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE

AccessStatsMsr

R/W

Map the guest's internal partition statistics page

0x400000E2

HV_X64_MSR_STATS_VP_RETAIL_PAGE

AccessStatsMsr

R/W

Map the guest's retail VP statistics page

0x400000E3

HV_X64_MSR_STATS_VP_INTERNAL_PAGE

AccessStatsMsr

R/W

Map the guest's internal VP statistics page

0x400000F0

HV_X64_MSR_GUEST_IDLE

AccessGuestIdleMsr

R

Trigger the guest's transistion to the idle power state