Microsoft Hypervisor CPUID Leaves

0x40000000

Hypervisor CPUID leaf range and vendor identifier signatures are returned in the following registers.

EAX

The maximum input value for hypervisor CPUID information. For Microsoft hypervisors, this value will be at least 0x40000005. The vendor ID signature should be used only for reporting and diagnostic purposes.

EBX

0x7263694D--"Micr"

ECX

0x666F736F--"osof"

EDX

0x76482074--"t Hv"

0x40000001

Hypervisor vendor-neutral interface identification, which determines the semantics of leaves from 0x40000002 through 0x400000FF, is returned in the following registers.

EAX

0x31237648--"Hv#1"

EBX

Reserved

ECX

Reserved

EDX

Reserved

0x40000002

Hypervisor system identity. These values will be zero until the operating system identity MSR is set. For more information about identifying a guest operating system, see Reporting the Identity of a Guest Operating System. After the operating system identity MSR is set, these values have the following definitions.

EAX

Build number

EBX

Bits 31-16: Major version

Bits 15-0: Minor version

ECX

Service pack

EDX

Bits 31-24: Service branch

Bits 23-0: Service number

0x40000003

Feature identification on EAX indicates the features that are available to the partition based on the current partition privileges.

EAX

Bit 0: VP run time (HV_X64_MSR_VP_RUNTIME) is available.

Bit 1: Partition reference counter (HV_X64_MSR_TIME_REF_COUNT) is available.

Bit 2: Basic SynIC MSRs (HV_X64_MSR_SCONTROL through HV_X64_MSR_EOM and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15) are available.

Bit 3: Synthetic timer MSRs (HV_X64_MSR_STIMER0_CONFIG through HV_X64_MSR_STIMER3_COUNT) are available.

Bit 4: APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) are available.

Bit 5: Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) are available.

Bit 6: Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) is available.

Bit 7: Virtual system reset MSR (HV_X64_MSR_ RESET) is available.

Bits 8-31: Reserved

Feature identification on EBX indicates the flags that a parent partition specified to create a child partition. The format is the same as that of the HV_PARTITION_PRIVILEGE_MASK structure.

EBX

Bit 0: CreatePartitions

Bit 1: AccessPartitionId

Bit 2: AccessMemoryPool

Bit 3: AdjustMessageBuffers

Bit 4: PostMessages

Bit 5: SignalEvents

Bit 6: CreatePort

Bit 7: ConnectPort

Bit 8: AccessStats

Bit 9 and 10: Reserved

Bit 11: Debugging

Bit 12: CPUManagement

Bit 13: ConfigureProfiler

Bits 14-31: Reserved

Feature identification on ECX contains information related to power management.

ECX

Bits 0-3: Maximum processor power state: 0 is C0, 1 is C1, 2 is C2, 3 is C3.

Bits 4-31: Reserved.

Feature identification on EDX indicates the miscellaneous features that are available to the partition.

EDX

Bit 0: The MWAIT instruction is available. For more information about MWAIT, see MONITOR and MWAIT.

Bit 1: Guest debugging support is available.

Bit 2: Performance monitor support is available.

Bit 3: Support for CPU dynamic partitioning events is available.

Bit 4: Support for passing hypercall input parameter block via XMM registers is available.

Bit 5: Support for a virtual guest idle state is available.

Bits 6-31: Reserved.

0x40000004

Implementation recommendations that are returned in the following registers indicate the behavior that the hypervisor recommends that the operating system implement for optimal performance.

EAX

Bit 0: Hypervisor recommends that the operating system use hypercalls for address space switches instead of using MOV to CR3 instruction.

Bit 1: Hypervisor recommends that the operating system use hypercalls for local TLB flushes instead of using INVLPG or MOV to CR3 instructions.

Bit 2: Hypervisor recommends that the operating system use hypercalls for remote TLB flushes instead of using inter-processor interrupts.

Bit 3: Hypervisor recommends that the operating system use MSRs to access APIC registers EOI, ICR, and TPR instead of using their memory-mapped counterparts.

Bit 4: Hypervisor recommends that the operating system use the hypervisor-provided MSR to initiate a system RESET.

Bit 5: Hypervisor recommends that the operating system use relaxed timing for this partition.

Bit 6-31: Reserved

EBX

The recommended number of attempts to retry a spinlock failure before notifying the hypervisor about the failure.

0xFFFFFFFF indicates never to retry.

ECX

Reserved.

EDX

Reserved.

0x40000005

Implementation limits are returned in the following register. If any value is zero, the hypervisor does not expose the corresponding information. Otherwise, the implementation limits have the following meanings.

EAX

The maximum number of virtual processors that the hypervisor supports.

EBX

The maximum number of logical processors that the hypervisor supports.

ECX

Reserved.

EDX

Reserved.

0x40000006

Implementation hardware features that have been detected and are currently in use by the hypervisor. These hardware-specific features are specified in the following registers.

EAX

Bit 0: Support for APIC overlay assist is detected and in use.

Bit 1: Support for MSR bitmaps is detected and in use.

Bit 2: Support for architectural performance counters is detected and in use.

Bit 3: Support for second-level address translation is detected and in use.

Bits 4-31: Reserved for future Intel-specific features.

EBX

Reserved.

ECX

Reserved.

EDX

Reserved for future AMD-specific features.