HV_CPUID_RESULT union

The HV_CPUID_RESULT union identifies the result of a CPUID instruction.

Syntax


typedef union _HV_CPUID_RESULT {
  struct {
    UINT32 Eax;
    UINT32 Ebx;
    UINT32 Ecx;
    UINT32 Edx;
  };
  UINT32                     AsUINT32[4];
  struct {
    UINT32 ReservedEax;
    UINT32 ReservedEbx  :24;
    UINT32 InitialApicId  :8;
    UINT32 ReservedEcx  :31;
    UINT32 HypervisorPresent  :1;
    UINT32 ReservedEdx;
  } VersionAndFeatures;
  struct {
    UINT32 MaxFunction;
    UINT8  VendorName[12];
  } HvVendorAndMaxFunction;
  struct {
    UINT32 Interface;
    UINT32 ReservedEbx;
    UINT32 ReservedEcx;
    UINT32 ReservedEdx;
  } HvInterface;
  HV_HYPERVISOR_VERSION_INFO MsHvVersion;
  struct {
    HV_PARTITION_PRIVILEGE_MASK PartitionPrivileges;
    UINT32                      MaxSupportedCState  :4;
    UINT32                      Reserved  :28;
    UINT32                      MwaitAvailable  :1;
    UINT32                      GuestDebuggingAvailable  :1;
    UINT32                      PerformanceMonitorsAvailable  :1;
    UINT32                      CpuDynamicPartitioningAvailable  :1;
    UINT32                      XmmRegistersForFastHypercallAvailable  :1;
    UINT32                      GuestIdleAvailable  :1;
    UINT32                      Reserved1  :26;
  } MsHvFeatures;
  struct {
    UINT32 UseHypercallForAddressSpaceSwitch  :1;
    UINT32 UseHypercallForLocalFlush  :1;
    UINT32 UseHypercallForRemoteFlush  :1;
    UINT32 UseApicMsrs  :1;
    UINT32 UseMsrForReset  :1;
    UINT32 UseRelaxedTiming  :1;
    UINT32 Reserved  :26;
    UINT32 LongSpinWaitCount;
    UINT32 ReservedEcx;
    UINT32 ReservedEdx;
  } MsHvEnlightenmentInformation;
  struct {
    UINT32 MaxVirtualProcessorCount;
    UINT32 MaxLogicalProcessorCount;
    UINT32 ReservedEcx;
    UINT32 ReservedEdx;
  } MsHvImplementationLimits;
} HV_CPUID_RESULT, *PHV_CPUID_RESULT;

Members

Eax

A 32-bit value in the EAX register.

Ebx

A 32-bit value in the EBX register.

Ecx

A 32-bit value in the ECX register.

Edx

A 32-bit value in the EDX register.

AsUINT32

A member in the union that can hold an array of four 32-bit values.

VersionAndFeatures

The results of the CPUID instruction with an input (EAX register) value of 1. For more information about this instruction, see Determining If Hypervisor Is Installed

ReservedEax: Reserved for the EAX register.
ReservedEbx: Reserved part (24 bits) of the EBX register.
InitialApicId: Part (8 bits) of the EBX register that holds the initial APIC identifier.
ReservedEcx: Reserved part (first 31 bits) of the ECX register.
HypervisorPresent: Part (last bit) of the ECX register that determines whether the hypervisor is present
ReservedEdx: Reserved for the EDX register.

HvVendorAndMaxFunction

The results of the CPUID instruction with an input (EAX register) value of 0x40000000 in the following members:

MaxFunction: The maximum input value for hypervisor CPUID information in the EAX register.
VendorName: The vendor identifier signature in the EBX, ECX, and EDX registers. The vendor is identified as Microsoft through the HV_CPUID_HV_VENDOR_MICROSOFT_EBX ('rciM'), HV_CPUID_HV_VENDOR_MICROSOFT_ECX ('foso'), and HV_CPUID_HV_VENDOR_MICROSOFT_EDX ('vH t') constants.

HvInterface

The hypervisor vendor-neutral interface identification. The results of the CPUID instruction with an input (EAX register) value of 0x40000001 in the following members:

Interface: The hypervisor interface signature in the EAX register. The signature is identified as the Microsoft hypervisor interface through the HvMicrosoftHypervisorInterface value of the HV_HYPERVISOR_INTERFACE enumeration.
ReservedEbx: Reserved for the EBX register.
ReservedEcx: Reserved for the ECX register.
ReservedEdx: Reserved for the EDX register.

MsHvVersion

The results of the CPUID instruction with an input (EAX register) value of 0x40000002 in an HV_HYPERVISOR_VERSION_INFO structure that identifies the version of the hypervisor. The version information is in the EAX, EBX, ECX, and EDX registers.

MsHvFeatures

The hypervisor feature identification. The results of the CPUID instruction with an input (EAX register) value of 0x40000003 in the following members:

PartitionPrivileges: An HV_PARTITION_PRIVILEGE_MASK union that identifies the synthetic MSRs and hypercalls that a partition can access. Partition privileges are in the EAX and EBX registers.
MaxSupportedCState: Part (4 bits) of the ECX register that holds the maximum processor power state.
Reserved: Reserved part (28 bits) of the ECX register.
MwaitAvailable: Part (first bit) of the EDX register that determines whether the MWAIT instruction is available.
GuestDebuggingAvailable: Part (second bit) of the EDX register that determines whether guest debugging support is available.
PerformanceMonitorsAvailable: Part (third bit) of the EDX register that determines whether performance monitor support is available.
CpuDynamicPartitioningAvailable: Part (fourth bit) of the EDX register that determines whether CPU dynamic partitioning support is available.
XmmRegistersForFastHypercallAvailable: Part (fifth bit) of the EDX register that determines whether XMM registers for fast hypercall support is available.
GuestIdleAvailable: Part (sixth bit) of the EDX register that determines whether support for the guest's transistion to the idle power state is available.
Reserved1: Reserved part (last 26 bits) of the EDX register.

MsHvEnlightenmentInformation

The recommendations from the hypervisor for the guest operating system to implement for optimal performance. The results of the CPUID instruction with an input (EAX register) value of 0x40000004 in the following members:

UseHypercallForAddressSpaceSwitch: Part (first bit) of the EAX register that determines whether the guest should use hypercall for address space switches instead of using MOV to CR3 instruction.
UseHypercallForLocalFlush: Part (second bit) of the EAX register that determines whether the guest should use hypercall for local TLB flushes instead of using INVLPG or MOV to CR3 instructions.
UseHypercallForRemoteFlush: Part (third bit) of the EAX register that determines whether the guest should use hypercall for remote TLB flushes instead of using interprocessor interrupts.
UseApicMsrs: Part (fourth bit) of the EAX register that determines whether the guest should use MSRs to access APIC registers EOI, ICR, and TPR instead of using their memory-mapped counterparts.
UseMsrForReset: Part (fifth bit) of the EAX register that determines whether the guest should use the hypervisor-provided MSR to initiate a system RESET.
UseRelaxedTiming: Part (sixth bit) of the EAX register that determines whether the guest should use relaxed timing for this partition.
Reserved: Reserved part (last 26 bits) of the EAX register.
LongSpinWaitCount: The recommended number of attempts to retry a spinlock failure before notifying the hypervisor about the failure in the EBX register.
ReservedEcx: Reserved for the ECX register.
ReservedEdx: Reserved for the EDX register.

MsHvImplementationLimits

Implementation limits imposed by the hypervisor. The results of the CPUID instruction with an input (EAX register) value of 0x40000005 in the following members:

MaxVirtualProcessorCount: The maximum number of virtual processors that the hypervisor supports in the EAX register.
MaxLogicalProcessorCount: The maximum number of physical processors that the hypervisor supports in the EBX register.
ReservedEcx: Reserved for the ECX register.
ReservedEdx: Reserved for the EDX register.

Remarks

For more information about results of CPUID instructions, see Microsoft Hypervisor CPUID Leafs.

Requirements

Header	Hvgdk.h (include Hvgdk.h)

HV_CPUID_RESULT union

Syntax

Members

Remarks

Requirements

See also