SIMP Register
- At virtual processor creation time and upon processor reset, the value of this synthetic interrupt message page (SIMP) register is 0x0000000000000000. Therefore, the SIMP is disabled by default. The guest must enable it by setting bit 0. If the specified base address is beyond the end of the partition's GPA space, the SIMP page will not be accessible to the guest. When modifying the register, guests should preserve the value of the reserved bits (1 through 11) for future compatibility. The guest uses an HV_SYNIC_SIMP union to program a SIMP register.
| 63:12 | 11:1 | 0 |
|---|---|---|
|
SIMP Base Address |
RsvdP |
Enable |
| Bits | Description | Attributes |
|---|---|---|
|
63:12 |
Base address (in GPA space) of SIMP (low 12 bits assumed to be zero) |
Read/write |
|
11:1 |
RsvdP (value should be preserved) |
Read/write |
|
0 |
SIMP enable |
Read/write |
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Build date: 11/16/2013
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