SIM and SIEF Pages
The SynIC defines two pages that extend the functionality of a traditional APIC. The addresses for these two pages are specified by the SIEFP register and the SIMP register. For more information about these register formats, see SynIC MSRs.
The SIEF and SIM pages are implemented as GPA overlay pages. For more information about overlay pages, see GPA Overlay Pages.
The addresses of the SIEF and SIM pages should be unique for each virtual processor. Programming these pages to overlap other instances of the SIEF or SIM pages or any other overlay page (for example, the hypercall page) will result in undefined behavior.
The hypervisor implements the SIEF and SIM pages so that a SIEF or SIM instance that is associated with a virtual processor is not accessible to other virtual processors. In such implementations, an access by one virtual processor to another virtual processor's SIEF or SIM page will result in a #MC fault. Guest operating systems should avoid performing such accesses.
Read and write accesses by a virtual processor to the SIEF and SIM pages behave like read and write accesses to RAM. However, the hypervisor's SynIC implementation also writes to these pages in response to certain events.
When the hypervisor creates or resets a virtual processor, the hypervisor clears SIEF and SIM pages to zero.
The SIEF page consists of a 16-element array of 256-byte event flags. For more information about these event flags, see Inter-Partition Communication Data Types. Each array element corresponds to a single synthetic interrupt source (SINTx).
The SIM page consists of a 16-element array of 256-byte messages. For more information about messages, see the HV_MESSAGE structure. Each array element (also known as a message slot) corresponds to a single synthetic interrupt source (SINTx). A message slot is said to be empty if the message type of the message in the slot is equal to HvMessageTypeNone from the HV_MESSAGE_TYPE enumeration.
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Build date: 11/16/2013