Memory Accesses

The behavior of instructions that access memory might differ from the behavior of the same instructions on a logical processor. This fact is the result of the hypervisor's physical memory virtualization mechanisms and of the existence of address ranges with special semantics (hypervisor call page or SynIC area). In a broad sense, this fact applies to all instructions because the processor fetches instructions from memory. However, this fact applies in particular to instructions with memory operands.

The following pseudo-code defines the different behaviors that can result from an access by a virtual processor to the virtual processor partition's GPA space. The pseudo-code assumes that a GPA memory access has been performed directly (that is, an explicit memory operand) or indirectly (an implicit access) by a virtual processor. The access is one of three types: Read, Write, and Execute (Instruction Fetch).

if the address is within an overlay page {
  if the access type is not allowed for the page {
  Generate #MC fault within guest
  }
  else {
    Perform access
  }
}
else if the address is within an unmapped GPA page {
 if the partition is the root partition {
 Allow the access to proceed to identity-mapped SPA
 }
 else {
 Suspend VP and send message to parent (unmapped GPA)
 }
}
else if the address is within a mapped GPA and
 the access type violates the mapping's access rights {
  if the partition is the root partition {
  Generate #MC fault in root
  }
  else {
  Suspend VP and send message to parent (GPA access right)
  }
}
else {
 Memory access proceeds normally 
}

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Build date: 11/16/2013