Time Stamp Counter

The time stamp counter (TSC) is virtualized for each virtual processor. Generally, the TSC value continues to run while a virtual processor is suspended.

Seamless TSC virtualization is not feasible on the x64 architecture. TSC virtualization is typically implemented through a simple TSC bias (an offset that is added to the logical processor's TSC). The hypervisor will attempt to prevent the TSC from jumping forward or backward as a virtual processor is scheduled on different logical processors. However, the hypervisor cannot compensate for situations where the TSC for a logical processor is set to zero by an SMI handler or as part of placing a logical processor into a low-power state. Furthermore, the TSC increment rate might slow down or speed up depending on thermal or performance throttling, over which the hypervisor has no control.

Guest software should only use the TSC for measuring short durations. Even when using the TSC in this simple way, algorithms should be resilient to sudden jumps forward or backward in the TSC value.

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Build date: 11/16/2013