Virtual Processor Register Formats
The hypervisor defines the following register formats for virtual processors.
Suspend Registers
The hypervisor recognizes two registers that allow a virtual processor to be suspended or unsuspended. Two registers are specified so callers can easily set or clear the two values independently. Unlike most registers, these registers are not defined by the underlying processor architecture and cannot be accessed by the virtual processor with which they are associated.
The first register is HvRegisterExplicitSuspend (from the HV_REGISTER_NAME enumeration). A caller uses HvRegisterExplicitSuspend and the HV_EXPLICIT_SUSPEND_REGISTER union in a call to the HvSetVpRegisters function to explicitly suspend the virtual processor.
The second register is HvRegisterInterceptSuspend (from the HV_REGISTER_NAME enumeration). The hypervisor sets HvRegisterInterceptSuspend to suspend a virtual processor because of an intercept. A caller can use the HV_INTERCEPT_SUSPEND_REGISTER union in a call to the HvSetVpRegisters function to suspend or unsuspend the virtual processor because of an intercept. The caller can clear bits in the HvRegisterInterceptSuspend register together or independently. Note that only the hypervisor can set bits that are clear; any attempt by a guest to set them will result in an error.
The HvRegisterInterceptSuspend register also contains a bit that is used to inhibit the virtual processor's TLB from being flushed from another processor by using the HvFlushVirtualAddressSpace or HvFlushVirtualAddressList hypercalls. If such an attempt is made while the flush inhibit bit (TlbLocked) is set, the caller's virtual processor will be suspended. When the flush inhibit bit is cleared, all other virtual processors that are suspended by an attempt to flush that virtual processor's TLB will be unsuspended. For more information about TLB flush restrictions, see Restrictions on TLB Flushes.
Virtual Processor Run Time Register
The hypervisor's scheduler internally tracks how much time each virtual processor consumes in executing code (both guest and hypervisor code). This cumulative time is accessible through the 64-bit read-only HV_X64_MSR_VP_RUNTIME hypervisor MSR. The time quantity is measured in 100ns units. HV_X64_MSR_VP_RUNTIME is defined as follows:
#define HV_X64_MSR_VP_RUNTIME 0x40000010
Interrupt State Register
The HvX64RegisterInterruptState register provides information about the interrupt state of the virtual processor. HvX64RegisterInterruptState indicates whether the virtual processor is in an interrupt shadow and whether non-maskable interrupts are currently masked. Certain instructions inhibit the delivery of hardware interrupts and debug traps for one instruction. Furthermore, when a non-maskable interrupt is delivered to the virtual processor, subsequent non-maskable interrupts are masked until the virtual processor executes an IRET instruction.
HvX64RegisterInterruptState is encoded with a HV_X64_INTERRUPT_STATE_REGISTER union.
Pending Interruption Register
The HvX64RegisterPendingInterruption register is used to indicate whether a pending interruption exists for the virtual processor. An interruption is defined as any event that is delivered through the virtual processor's interrupt descriptor table (for example, exceptions, interrupts, or debug traps). If an interruption is pending, the hypervisor will generate the interruption when the virtual processor resumes execution. This allows code that runs within the parent partition, for example, to respond to an MSR intercept by generating a general protection fault.
If an intercept is generated during the delivery of an interruption, the hypervisor holds the interruption as pending and sends an intercept message to the parent partition. The parent partition can resolve the intercept and resume the virtual processor. In this situation, the hypervisor will redeliver the interruption.
The type of a pending interruption is encoded with the HV_X64_PENDING_INTERRUPTION_TYPE enumeration.
The pending interruption register is formatted with the HV_X64_PENDING_INTERRUPTION_REGISTER union.
Floating-point and Vector Registers
Floating point registers are encoded as 80-bit values with the HV_X64_FP_REGISTER union.
Additional status and control information for the floating point and vector units are stored in particular formats by using the HV_X64_FP_CONTROL_STATUS_REGISTER and HV_X64_XMM_CONTROL_STATUS_REGISTER unions.
Segment Registers
Segment register state is encoded with the HV_X64_SEGMENT_REGISTER structure.
The limit is encoded as a 32-bit value in the Limit member of HV_X64_SEGMENT_REGISTER. For x64-long-mode segments, the limit is ignored. For legacy x86 segments, the limit must be expressible within the bounds of the x64 processor architecture. For example, if the Granularity member of HV_X64_SEGMENT_REGISTER is set within the attributes of a code or data segment, the low-order 12 bits of the limit must be 1s.
The Present member of HV_X64_SEGMENT_REGISTER controls whether the segment acts like a null segment (that is, whether a memory access performed through that segment generates a #GP fault).
The MSRs IA32_FS_BASE and IA32_GS_BASE are not defined in a list of MSRs because they are aliases to the Base member of HV_X64_SEGMENT_REGISTER. You should use the HvX64RegisterFs and HvX64RegisterGs registers (from the HV_REGISTER_NAME enumeration) and HV_X64_SEGMENT_REGISTER instead.
Table Registers
Table registers are similar to segment registers. However, table registers have no selector or attributes, and the limit is restricted to 16 bits. Table register state is encoded with the HV_X64_TABLE_REGISTER structure.
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Build date: 11/16/2013