HV_INTERCEPT_SUSPEND_REGISTER union

The HV_INTERCEPT_SUSPEND_REGISTER union identifies how the HvRegisterInterceptSuspend register is encoded.

Syntax

typedef union _HV_INTERCEPT_SUSPEND_REGISTER {
  UINT64 AsUINT64;
  struct {
    UINT64 Suspended  :1;
    UINT64 TlbLocked  :1;
    UINT64 Reserved  :62;
  };
} HV_INTERCEPT_SUSPEND_REGISTER, *PHV_INTERCEPT_SUSPEND_REGISTER;

Members

AsUINT64

A member in the union that can hold one 64-bit value that identifies how the HvRegisterInterceptSuspend register is encoded.

Suspended

A UINT64 value that specifies whether to suspend or unsuspend the virtual processor because of an intercept. Setting this member is equivalent to setting the first bit of the 64-bit AsUINT64 member (0x0000000000000001).

TlbLocked

A UINT64 value that specifies whether a caller can inhibit the virtual processor's TLB from being flushed from another processor by using the HvFlushVirtualAddressSpace or HvFlushVirtualAddressList hypercalls. Setting this member is equivalent to setting the second bit of the 64-bit AsUINT64 member (0x0000000000000002).

Reserved

This member is reserved and should be set to zero. Setting this member to zero is equivalent to setting the remaining 62 bits (0xFFFFFFFFFFFFFFFC) of the 64-bit AsUINT64 member to zeros.

Remarks

A caller can use the HV_INTERCEPT_SUSPEND_REGISTER union in a call to the HvSetVpRegisters hypercall to suspend or unsuspend the virtual processor because of an intercept. The caller can clear bits in the HvRegisterInterceptSuspend register together or independently. Note that only the hypervisor can set bits that are clear; any attempt by a guest to set them will result in an error. For more information about suspending a virtual processor, see Virtual Processor States.

The HvRegisterInterceptSuspend register also contains a bit that is used to inhibit the virtual processor's TLB from being flushed from another processor using the HvFlushVirtualAddressSpace or HvFlushVirtualAddressList hypercall. If such an attempt is made while the flush inhibit bit (TlbLocked) is set, the caller's virtual processor will be suspended. When the flush inhibit bit is cleared, all other virtual processors that were suspended by an attempt to flush that virtual processor's TLB will be unsuspended. For more information about TLB flush restrictions, see Restrictions on TLB Flushes.

Requirements

See also

HvFlushVirtualAddressList

HvFlushVirtualAddressSpace

HvSetVpRegisters

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Build date: 11/16/2013