HV_X64_INTERRUPT_STATE_REGISTER union
The HV_X64_INTERRUPT_STATE_REGISTER union identifies how the HvX64RegisterInterruptState register is encoded.
Syntax
typedef union _HV_X64_INTERRUPT_STATE_REGISTER { UINT64 AsUINT64; struct { UINT64 InterruptShadow :1; UINT64 NmiMasked :1; UINT64 Reserved :62; }; } HV_X64_INTERRUPT_STATE_REGISTER, *PHV_X64_INTERRUPT_STATE_REGISTER;
Members
- AsUINT64
-
A member in the union that can hold one 64-bit value that identifies whether the virtual processor is in an interrupt shadow and whether non-maskable interrupts are currently masked.
- InterruptShadow
-
A UINT64 value that specifies whether the virtual processor is in an interrupt shadow. Setting this member is equivalent to setting the first bit of the 64-bit AsUINT64 member (0x0000000000000001).
- NmiMasked
-
A UINT64 value that specifies whether non-maskable interrupts are currently masked. Setting this member is equivalent to setting the second bit of the 64-bit AsUINT64 member (0x0000000000000002).
- Reserved
-
This member is reserved and should be set to zero. Setting this member to zero is equivalent to setting the remaining 62 bits (0xFFFFFFFFFFFFFFFC) of the 64-bit AsUINT64 member to zeros.
Remarks
The HvX64RegisterInterruptState register provides information about the interrupt state of the virtual processor. HvX64RegisterInterruptState indicates whether the virtual processor is in an interrupt shadow and whether non-maskable interrupts are currently masked. Certain instructions inhibit the delivery of hardware interrupts and debug traps for one instruction. Furthermore, when a non-maskable interrupt is delivered to the virtual processor, subsequent non-maskable interrupts are masked until the virtual processor executes an IRET instruction.
The HV_X64_INTERRUPT_STATE_REGISTER union is used in the HV_REGISTER_VALUE union.
Requirements
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See also
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Build date: 11/16/2013