HV_X64_MSR_STIMER_CONFIG_CONTENTS structure

The HV_X64_MSR_STIMER_CONFIG_CONTENTS structure describes encoding for the synthetic timer configuration.

Syntax

typedef struct _HV_X64_MSR_STIMER_CONFIG_CONTENTS {
  union {
    UINT64 AsUINT64;
    struct {
      UINT64 Enable  :1;
      UINT64 Periodic  :1;
      UINT64 Lazy  :1;
      UINT64 AutoEnable  :1;
      UINT64 ReservedZ1  :12;
      UINT64 SINTx  :4;
      UINT64 ReservedZ2  :44;
    };
  };
} HV_X64_MSR_STIMER_CONFIG_CONTENTS, *PHV_X64_MSR_STIMER_CONFIG_CONTENTS;

Members

AsUINT64

A member in the union that can hold one 64-bit value that describes encoding for synthetic timer configuration.

Enable

A UINT64 value that indicates whether the synthetic timer is enabled. When Enable is set, the timer is enabled. Setting this member is equivalent to setting the first bit (bit 0) of the 64-bit AsUINT64 member (0x0000000000000001).

Periodic

A UINT64 value that indicates whether the synthetic timer is periodic. When Periodic is set, the timer recurs at specific intervals. When Periodic is clear, the timer occurs only once. Setting this member is equivalent to setting the second bit (bit 1) of the 64-bit AsUINT64 member (0x0000000000000002).

Lazy

A UINT64 value that indicates whether the synthetic timer is lazy (that is, the timer signal is deferred until the virtual processor is available, or the timer signal might be skipped entirely). When Lazy is set, the timer is lazy. When Lazy is clear, the timer is not lazy. Setting this member is equivalent to setting the third bit (bit 2) of the 64-bit AsUINT64 member (0x0000000000000004).

AutoEnable

A UINT64 value that indicates whether the Enable bit is automatically set. When AutoEnable is set, writing a nonzero value to the corresponding timer count register causes the Enable bit to be set and activates the counter. When AutoEnable is clear, Enable should be set after writing the corresponding count register in order to activate the counter. Setting this member is equivalent to setting the fourth bit (bit 3) of the 64-bit AsUINT64 member (0x0000000000000008).

ReservedZ1

This member is reserved and should be set to zero. Setting this member to zero is equivalent to setting each of bits 4 through 15 (0x000000000000FFF0) of the 64-bit AsUINT64 member to zero.

SINTx

A UINT64 value that indicates the synthetic interrupt source. The synthetic interrupt source value is set in bits 16 through 19 of the 64-bit AsUINT64 member (0x00000000000F0000).

ReservedZ2

This member is reserved and should be set to zero. Setting this member to zero is equivalent to setting each of the remaining 44 bits (0xFFFFFFFFFFF00000) of the 64-bit AsUINT64 member to zero.

Remarks

For more information about how synthetic timer configuration registers are encoded, see Synthetic Timer Configuration Register.

Requirements

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Build date: 11/16/2013